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Nanoxplore synthesis does not works when using abc9 flow
pending-verification
This issue is pending verification and/or reproduction
#4606
opened Sep 19, 2024 by
samhanic
Port names starting with '%' cause stack buffer overflow during error reporting
pending-verification
This issue is pending verification and/or reproduction
#4599
opened Sep 13, 2024 by
mattyoung101
verific: wrong source attribute for $add cell with binary literal operand
pending-verification
This issue is pending verification and/or reproduction
#4597
opened Sep 12, 2024 by
RCoeurjoly
Inconsistency with how libyosys is imported in Python
feature-request
#4591
opened Sep 9, 2024 by
donn
Synthesis with synth_xilinx crashes in TECHMAP pass
pending-verification
This issue is pending verification and/or reproduction
#4590
opened Sep 9, 2024 by
marzoul
Problems with 3 bit add not passing eqy
pending-verification
This issue is pending verification and/or reproduction
#4573
opened Aug 30, 2024 by
oharboe
ASTNode::simplify has supralinear performance with deep nesting of expressions
pending-verification
This issue is pending verification and/or reproduction
#4562
opened Aug 22, 2024 by
whitequark
Cannot select and cutpoint blackbox modules
pending-verification
This issue is pending verification and/or reproduction
#4561
opened Aug 22, 2024 by
RCoeurjoly
Double free on exit when design is saved (pyosys+gcc LTO only)
pending-verification
This issue is pending verification and/or reproduction
#4535
opened Aug 13, 2024 by
ACharlyR
memory_libmap creates dangling pins
pending-verification
This issue is pending verification and/or reproduction
#4529
opened Aug 7, 2024 by
gzz2000
ERROR: Can't open ABC output file.
pending-verification
This issue is pending verification and/or reproduction
#4522
opened Aug 5, 2024 by
exhaust-create
Support quoted strings as arguments to passes
feature-request
#4511
opened Jul 26, 2024 by
gussmith23
Autoname seems to get stuck in a loop and consume all the memory on the system
pending-verification
This issue is pending verification and/or reproduction
#4509
opened Jul 25, 2024 by
QuantamHD
Add support/workaround for flattening
inout
port with tri-state signals
feature-request
#4501
opened Jul 21, 2024 by
Rodrigodd
Custom Yosys Passes Result in Faulty Synthesis and Simulation Errors
pending-verification
This issue is pending verification and/or reproduction
#4491
opened Jul 15, 2024 by
LoSyTe
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